OVERVIEW
FPDP HISTORY
FPDP FEATURES
The Front Panel Data Port (FPDP) is a platform-independent 32-bit synchronous data flow path that allows data to be transfered at high speeds (160 MBytes/sec.) over moderate distances between boards and processing blocks. Pioneered by Interactive Circuits and Systems Ltd., FPDP is a cost effective solution to most data-transfer problems, and it eliminates issues of contention and limited bandwidth. It is also the only interconnect standad that allows box-to-box data transfer.
The use of differential PECL strobe (clock) signals eliminates the "glitch" problem and allows the source and destination to be separated by over 10 feet. The SYNC signal is repeated at the end of every frame of data (Repeating Frame Data Mode). For multi-channel data, this assures that the channel synchronization can be maintained in every frame of data.
FPDP had its beginnings in the late 1980s when Sky Computers Inc. came out with the SKYburst concept. SKYburst, which was a front panel 32-bit parallel I/O port that used a ribbon cable to connect to other boards, was also supported by ICS in its ICS-140 ADC product. Soon afterward, Mercury Computers introduced the similar I/OTTL80. 

In 1994, ICS introduced the FPDP, a significantly improved version of these technologies. FPDP allowed sustained data throughput of up to 160MBytes/s. By using PECL Data Strobe drivers, the interconnect cables could span more than 10 feet. Furthermore, the FPDP connector cable could be bussed across multiple boards. 

In 1995, ICS decided to seek standardization of FPDP through the VMEbus Industry Trade Association (VITA). Sky and Mercury immediately agreed to help draft the VITA-17 Standard, and were soon joined by CSP Inc. and Ariel Corporation.. During the standardization process, several other companies expressed interest in using FPDP, and since then, many partner companies have adopted FPDP as the high speed front panel interconnect of choice. 

At VITA's first annual Bus and Board Conference in San Jose, California, held on January 11th and 12th, 1999, ICS was presented with an award for the development and standardization of FPDP. Mr. Ray Alderman, Chairman of VITA, commended ICS for its "leadership in the development and promotion of FPDP as an open system standard" and "selfless" actions which "maximize[d] vendor participation for the sole benefit of end users." 

On February 11th, 1999, FPDP was approved as an American National Standard Institute (ANSI) Standard, ANSI/VITA-17. This was a landmark development for FPDP's acceptance as the preferred high-performance data transfer standard.

Low Cost and Easy Implementation
FPDP uses inexpensive ribbon cables to connect between boards and the interface occupies less than 1.5 square inches of board space.

Eliminates Backplane Bottleneck
FPDP does not use the backplane bus, thereby eliminating the issues of contention and limited bandwidth. This makes the sustained transfer rate and data bandwidth known for certain during the design stage, so costly bandwidth problems do not crop up during the system integration stage.

Interference Free
FPDP does not interfere with any other interfaces using the VMEbus P2 Connector, including RACEway, SKYchannel and VSB.

Minimal Software Required
Very little software interaction is required to interface different devices using FPDP. This is yet another factor contributing to the overall low cost of implementing FPDP.

Platform Independent
FPDP has now been introduced on  PCI Bus products, and is the fastest method of data transfer to your PC, with rates of up to 133MBytes/s.

Scalable Bandwidth
Multiple FPDPs on a single device allow for scalable data bandwidth, providing system designers with I/O bandwidth in excess of 2Gbits/s.

Bussable Between Boards
Many of FPDP's applications are in large data acquisition systems, where data from multiple channels must be acquired and processed. For this reason, FPDP is designed to be bussable between multiple boards. A framing mechanism was established such that each frame of data contains a single sample from each channel in the system. A single control line (Sync Pulse) was included in the design to identify the start and end of each frame.

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